stress test total un its units failure rate colors conditions device hrs. tested failed mtbf (% /1k hours) gap her/yellow, t a = 25c 32,000 32 0 32,000 3.125 alingap amber/ green, i f = 25 ma gap her/green, gap yellow/green, gap orange/green gap her/yellow, t a = 55c 88,000 88 0 88,000 1.14 alingap yellow/ green, i f = 5 ma gap her/green, gap yellow/green, gap orange/green gap her/yellow, t a = -40c 32,000 32 0 32,000 3.125 alingap yellow/ green, i f = 25 ma gap her/green, gap yellow/green, gap orange/green point typical performance description the following cumulative test results have been obtained from testing performed at avago technologies in accordance with the latest revisions of mil-std-883. avago technologies tests parts at the absolute maximum rated conditions recommended for the device. the actual performance you obtain from avago technologies parts depends on the electrical and environmental characteristics of your application but will probably be better than the performance outlined in table 1. table 1. life tests demonstrated performance HSMF-C153, hsmf-c155, hsmf-c156 and hsmf-c157 hsmf-c15x bicolor surface mount chip leds reliability data sheet
2 example of failure rate calculation assume a device operating 8 hours/day, 5 days/week. the utilization factor, given 168 hours/week is: (8 hours/day) x (5 days/week) / (168 hours/week) = 0.25 the point failure rate per year (8760 hours) at 25c ambient temperature is: (0.22% / 1k hours) x (0.25) x (8760 hours/year) = 0.482 % per year similarly, 90% confidence level failure rate per year at 25c: (0.55% / 1k hours) x (0.25) x (8760 hours/year) = 1.20% per year point typical performance performance in time [1] in time [2] (60% confidence) (90% confidence) ambient junction failure rate failure rate temperature (c) temperature (c) mtbf [1] (%/1k hours) mtbf [2] (%/1k hours) 85 90 67,500 1.48 26,900 3.72 75 85 81,000 1.23 32,200 3.11 65 81 97,800 1.02 38,900 2.57 55 76 118,600 0.84 47,200 2.12 45 66 180,800 0.55 72,000 1.39 35 56 282,900 0.35 112,600 0.89 25 46 455,300 0.22 181,200 0.55 table 2. reliability predictions (i f = 25 ma dc) demonstrated performance failure rate prediction the failure rate of semiconductor devices is determined by the junction temperature of the device. the relationship between ambient temperature and actual junction temperature is given by the following: t j (c) = t a (c) + ja p avg where t a = ambient temperature in c ja = thermal resistance of junction-to-ambient in c/ watt p avg = average power dissipated in watts the estimated mtbf and failure rate at temperatures lower than the actual stress temperature can be determined by using an arrhenius model for temperature acceleration. results of such calculations are shown in the table on the following page using an activation energy of 0.43 ev (reference mil-hdbk-217). notes: [1] the point typical mtbf (which represents 60% confidence level) is the total device hours divided by the number of failures. in the case of zero failures, one failure is assumed for this calculation. [2] the 90% confidence mtbf represents the minimum level of reliability performance which is expected from 90% of all samples. this confidence interval is based on the statistics of the distribution of failures. the assumed distribution of failures is exponen tial. this particular distribution is commonly used in describing useful life failures. refer to mil-std-690b for details on this methodo logy. [3] a failure is any led which does not emit light and maximum percent i v degradation is >50%.
3 units units test name reference test conditions tested failed temperature cycle mil-std-883 method 1010 -40c to 85c, 15 min. dwell, 5 min. transfer, air to air storage 5 cycles 2300 0 20 cycles 2300 0 50 cycles 2300 0 100 cycles 2800 2 open 300 cycles 2298 0 humidity 60c, 90% rh, 10 ma temperature cycle 240 hours 32 0 500 hours 32 0 1000 hours 32 0 temperature/humidity jis c 7021 meth. b-11, 60c, 90% rh, unbias storage cond. b 500 hours 50 0 high temperature jis c 7021 meth. b-10, 85c, unbias storage cond. c 1000 hours 50 0 low temperature jis c 7021 meth. b-12 -40c, unbias storage 1000 hours 50 0 solderability test jis c 7021 method a-2 230c 5c, 50 0 dwell time = 5 sec. 1 sec. solder resistance test 250c 15c, 50 0 dwell time = 5 sec. 1 sec. table 3. environmental tests (ir reflow solder processed at 230 5c for 10 seconds)
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies, limited in the united states and other countrie s. data subject to change. copyright ? 2006 avago technologies pte. all rights reserved. obsoletes 5989-1742en av01-0314en - july 14, 2006 floor life level reference precondition soak time 3xir time conditions 1 j-std-020a 85c/85% rh 168 hours 4 minor lifted da 1 year - 30c/85% rh 2a j-std-020a 85c/60% rh 120 hours 0 4 weeks - 30c/60% rh 3 j-std-020a 60c/60% rh 40 hours 0 168 hours - 30c/60% rh 4 j-std-020a 60c/60% rh 20 hours 0 72 hours - 30c/60% rh (b) electrical test data tmcl@ -40c / 85c floor life level reference 3xir 5x 20x time conditions 1 j-std-020a 0 0 0 1 year - 30c/85% rh 2a j-std-020a 0 0 0 4 weeks - 30c/60% rh 3 j-std-020a 0 0 0 168 hours - 30c/60% rh 4 j-std-020a 0 0 0 72 hours - 30c/60% rh conclusion: no functional failures were detected in all levels up to 20xtmcl. however, based on visual inspection data, minor lifted die-attach was found in lots that precondition with jedec level 1 which potentially can affect long term reliability. therefore, chip led was classified as a level 2a product. table 4. moisture sensitivity level characterization test matrix (a) visual inspection data
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